1. Field of Invention
The present invention relates to a LCOS (Liquid Crystal On Silicon) display field. More particularly, the present invention relates to a color LCOS display loading the R, G, and B data in a non-sequential pattern.
2. Description of Related Art
In a conventional color LCOS display driving system, a driving set of a level shifter, a Digital Analog Converter (DAC), and a unity-gain buffer is required for each R, G, and B data supplied to a pixel. Therefore, for example, if there are 80 pixels in a scan line, driving sets with total number of 240 may be required. This architecture significantly increases the manufacturing cost and complexity of the LCOS display driving system.
Recently, a color LCOS display driving system with shared components, such as a shared level shifter, a shared DAC, and a shared unity-gain buffer for all R, G, and B data supplied to a pixel is proposed. This type of LCOS display driving system employs a multiplexer and a demultiplexer for managing the R, G, and B data to the shared level shifter, the shared DAC, and shared buffer, so that separate driving sets for each R, G, and B data are no longer required. The color LCOS display driving system utilizing this approach is disclosed in U.S. Pat. No. 6,097,632, which is incorporated herein by reference.
FIG. 1 is a block diagram illustrating a color LCOS display driving system 100 with a shared driving set. The shift register 110 shifts a load signal from a data bus (not shown). A first R data latch 120A, first G data latch 120B, and first B data latch 120C latch the R, G, and B data from the data bus respectively while receiving the load signal from the shift register 110. A second R data latch 130A, second G data latch 130B, and second B data latch 130C further latch the R, G, and B data from the first R data latch 120A, first G data latch 120B, and first B data latch 120C, correspondingly.
The multiplexer 140 then multiplexes the R, G, and B data that one of them enters a shared level shifter 150 each time for shifting the level. The level shifted R, G, or B data are then transferred to a shared DAC 160 for converting the R, G, or B data to a corresponding analog R, G, or B data voltage. The shared unity-gain buffer 170 then follows the analog R, G, or B data voltages. Thereafter, the demultiplexer 180 demultiplexes the analog R, G, or B data voltage from the shared unity-gain buffer 170 and outputs to a corresponding pixel.
In the conventional LCOS display driving system 100, the multiplexer 140/demultiplexer 180 multiplexes/demultiplexes the R, G, and B data in a sequential pattern. That is, the loading sequences for all pixels in all scan lines are all identical. For example, R data is loaded to the shared level shifter 150 first, followed by the G data, and finally the B data. FIG. 2 shows a frame 200 comprising multiple scan lines 210. Each scan line 210 is comprised of even pixels 210A and odd pixels 210B both having the identical loading sequence, RGB. All even pixels 210A and odd pixels 210B in all scan lines of frame 200 have the same loading sequence RGB.
However, while the R, G, and B data are loaded in this sequential pattern, a so-called “data line floating” effect will arise, and dramatically interfere with the adjacent data, resulting in an erroneous display. FIG. 3 is a timing chart illustrating the “data line floating” effect while the R, G, and B data are loaded in a sequential pattern. As shown in the FIG. 3, while the scan line is turned on for sequential loading the R, G, and B data, the switch 1 of the multiplexer 140 is first turned on for loading the R data. Subsequently, the switch 2 of the multiplexer 140 is turned on for loading the G data. Finally, the switch 3 of the multiplexer 140 is turned on for loading the B data. The loading of G and B data both couples to the previously loaded R data, resulting in an incorrect R data level. Similarly, the level of the G data is be coupled by the following B data. These coupling effects between the R, G, and B data in a scan line will lead to an erroneous display of the R, G, and B data.
Besides, during the demultiplexing, a clock feed-through effect will also cause a faulty display. FIG. 4 shows a circuit diagram in the demultiplexer 180. The demultiplexer 180 has PMOS transistor 181 and capacitors Cov 182. While a clock signal 183 is supplied, the analog R, G, or B data voltage is entered the input 184, and output from the output 185. However, due to the clock feedthrough, the output analog R, G, or B data voltage will increase an undesired clock feedthrough voltage, ΔV, determined by the formula:
      Δ    ⁢                  ⁢    V    =                    V        ck            ×              WC        ov                            WC        ov            +      CH      
Where Vck is the clock signal voltage, Wcov is the capacitance of the capacitor Cov 182, and CH is the capacitance of the capacitor 186. The undesired clock feedthrough voltage ΔV can be as high as 50 mV. This clock feedthrough effect also results in an incorrect display and should be avoided.
For the forgoing reasons, there is a need for an improved LCOS display driving system and method that the coupling effect of between loaded data can be minimized. Besides, there is also a need for an improved LCOS display driving system and method that the clock feed-through effect can be avoided.